Pillar 1: Integrated Power Delivery for 2.5D/3D Heterogeneous Systems
• Proven Tape-out Track Record: Independently spearheaded the end-to-end design, tape-out, and experimental validation of 7 flip-chip PMICs, alongside co-designing and verifying 4 additional PMICs, maintaining a 100% silicon success rate.
• Methodology Leadership in SiP: Established an end-to-end design methodology for flip-chip PMICs and SiP integration, targeting reduced iteration cycles for complex multi-chiplet power delivery networks.
• Premier Solid-State Venue Impact: First-authored 3 flagship conference papers at IEEE CICC 2026 and IEEE ESSERC 2026. First-authored 2 regular papers in IEEE JSSC focusing on advanced IVR architectures.
Pillar 2: High-Efficiency Power Conversion & Intelligent Mixed-Signal Control
• Architectural & Topology Breakthroughs: Pioneered novel Hybrid/Resonant SC topologies and trajectory-based soft-switching control, pushing Pareto frontiers of volumetric power density and system efficiency.
• Domain-Specific Power Management: Chip implementation of a lightweight learning algorithm into SIMO converter control, achieving dynamic real-time cross-regulation mitigation.
• Power Electronics Track Record: Published 5 first-authored papers in IEEE APEC and IEEE COMPEL.
Pillar 3: Clocking-Power Co-Design, Dynamic Scaling & Resilient Architectures
• Proactive Power-Performance Scaling: Spearheaded instruction-driven proactive clocking and adaptive power management.
• Unified Power-and-Clock Regulation: Led the design of unified voltage-and-frequency regulators (UVFR) for energy-efficient computing.
• Top-Tier Publication Success: Published 4 first-authored papers, highlighted by IEEE TCAS-I and IEEE A-SSCC 2022.