Hello! I am Xuliang Wang
Post-Doctoral Fellow
Department of Electronic and Computer Engineering · Hong Kong University of Science and Technology
Power Semiconductors and Applications Center (PowerSAC) · Center Director: Chair Prof. Kevin Jing Chen (IEEE Fellow)
Mixed-signal PMIC design seamlessly integrated with 2.5D/3D advanced packaging — pioneering ultra-high-density, energy-efficient power delivery for next-generation AI computing, edge intelligence, and resilient semiconductor systems.
All publications, research interests, and career milestones from the CV.
X. Wang, T. Min, X. Liu, and K. J. Chen, “Octopus: a 5-mm-Height 337-W/in³ Resonant Converter Ring Featuring Saturation-Free Magnetic Flux and Reduced Resonant Capacitor Ripple via Quad-Phase Coupled Inductors,” APEC 2027 (Accepted as Lecture).
X. Wang et al., “A 0.73 A/mm³ Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator with Auxiliary-Assisted Gain Boosting for High-Density PoL Applications,” IEEE JSSC, vol. 61, no. 10, pp. 5825–5837, Oct. 2026.
W. Wu, …, X. Wang, et al., “A 256-316-GHz Frequency Quadrupler…,” ESSERC 2026 (Accepted as Lecture).
X. Men, R. Chen, …, X. Wang, et al., “A 280 MHz All-Digital Current-Mode IVR…,” ESSERC 2026 (Accepted as Lecture).
R. Chen, X. Men, …, X. Wang, et al., “An Autonomous Computational Current-Booster Chiplet for Fast Droop Mitigation…,” ESSERC 2026 (Accepted as Lecture).
X. Wang et al., “A 96.6%-Peak-Efficiency 4.63-A/mm³ Resonant-Tank Converter with RDL Trace Inductor and Trajectory Control for Vertical Power Delivery,” ESSERC 2026 (Accepted as Lecture).
X. Wang et al., “Mobius: A 12V-to-1V Charge-Cross-Converging Converter Ring with Monolithic Handshake Driving for Next-Generation AI Server,” ESSERC 2026 (Accepted as Lecture).
X. Wang et al., “A 6-A 93.8%-Peak-Efficiency 5V-to-Sub-1V Segment-Interlaced SC-Parallel-Inductor Converter Featuring Inherently Balanced Ganging for Wafer-Scale Computing System,” IEEE JSSC (Early Access), Aug. 2026.
Technical appendix figures — JSSC [J2, J3], ESSERC [C2, C3], CICC [C9], and TCAS-I [J1].
Switched-Capacitor-Stack-Inductor Volumetric IVR with Auxiliary-Assisted Gain Boosting for High-Density PoL Applications [J2].
6-A 93.8%-Peak-Efficiency Segment-Interlaced SC-Parallel-Inductor Converter for Wafer-Scale Computing [J3].
96.6%-Peak-Efficiency Resonant-Tank Converter with RDL Trace Inductor and Trajectory Control for Vertical Power Delivery [C3].
Mobius: A 12V-to-1V Charge-Cross-Converging Converter Ring with Monolithic Handshake Driving for Next-Generation AI Server [C2].
Unicorn: A Unified Clock-and-Power SoC with RL-Adapted Digital SIMO Control and In-TRO Frequency Boosting for Edge Computing [C9].
A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads [J1].
Conference milestones and travel albums — The Sun Never Sets, Echoes of Blue Hours, Wanderlust & Pathways.
At the IEEE European Solid-State Electronics Research Conference (ESSERC) in Mallorca — presenting Mobius and vertical power delivery research.
At the IEEE Workshop on Control and Modeling for Power Electronics (COMPEL) in Cambridge — presenting power-electronics research and serving as Session Chair.
At the IEEE Custom Integrated Circuits Conference (CICC) in Seattle — showcasing the Unicorn unified clock-and-power SoC and connecting with the IC design community.
Doctoral dissertation defense on the eve of Christmas 2022 at the Hong Kong University of Science and Technology — IR-Drop- and Timing-Aware Power Management Techniques for Microprocessors (supervisor: Prof. Wing-Hung Ki).
Core research line: Integrated Power Delivery for 2.5D/3D Heterogeneous Systems — Vertical Power Delivery (VPD), high-density PMIC & SiP, and package-integrated multiphase IVRs for AI accelerators and data centers.
Vertical Power Delivery (VPD) & SiP, package-integrated multiphase IVRs, and holistic circuit-package co-design for AI accelerators and data centers.
Research Focus: Architectures for chiplet systems including high-density Intermediate Bus Converters (IBC) and Point-of-Load (PoL) regulators; multiphase package-integrated regulators and flip-chip PMICs; systematic optimization framework pushing the Pareto frontier of volumetric power density and system efficiency.
Hybrid/resonant SC topologies, learning-based control, and SIMO cross-regulation mitigation for compact high-density systems.
Research Focus: Advanced Hybrid/Resonant Switched-Capacitor topologies for soft-switching high-density regulation; circuit-level model/learning-based control and transient-aware algorithms; Single-Inductor Multiple-Output (SIMO) architectures with active cross-regulation suppression.
Unified power-clock regulation, DVFS/MEP for ULP edge devices, IMC power-timing co-design, and circuit-level side-channel countermeasures.
Research Focus: Instruction-driven adaptive clocking, Unified Voltage-and-Frequency Regulators (UVFRs), and Minimum Energy Point (MEP) tracking; power-timing co-design for In-Memory Computing, voltage-stacked delivery, and WPT; integrated countermeasures for Power Side-Channel Attack.
Complete list from CV — conference papers [C1]–[C27] and journal papers [J1]–[J3].
Email: xwangef@connect.ust.hk
Phone: +86 15151856366
Office: CYT Building, The Hong Kong University of Science and Technology, Hong Kong SAR
Open to faculty positions and collaborative research on mixed-signal power management ICs, 3D ICs, and emerging power delivery solutions.