All entries from the CV: 30 publications · 4 research interests · 11 career/education milestones.
X. Wang, T. Min, X. Liu, and K. J. Chen, “Octopus: a 5-mm-Height 337-W/in³ Resonant Converter Ring Featuring Saturation-Free Magnetic Flux and Reduced Resonant Capacitor Ripple via Quad-Phase Coupled Inductors,” APEC 2027 (Accepted as Lecture).
X. Wang et al., “A 0.73 A/mm³ Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator with Auxiliary-Assisted Gain Boosting for High-Density PoL Applications,” IEEE JSSC, vol. 61, no. 10, pp. 5825–5837, Oct. 2026.
W. Wu, …, X. Wang, et al., “A 256-316-GHz Frequency Quadrupler…,” ESSERC 2026 (Accepted as Lecture).
X. Men, R. Chen, …, X. Wang, et al., “A 280 MHz All-Digital Current-Mode IVR…,” ESSERC 2026 (Accepted as Lecture).
R. Chen, X. Men, …, X. Wang, et al., “An Autonomous Computational Current-Booster Chiplet for Fast Droop Mitigation…,” ESSERC 2026 (Accepted as Lecture).
X. Wang et al., “A 96.6%-Peak-Efficiency 4.63-A/mm³ Resonant-Tank Converter with RDL Trace Inductor and Trajectory Control for Vertical Power Delivery,” ESSERC 2026 (Accepted as Lecture).
X. Wang et al., “Mobius: A 12V-to-1V Charge-Cross-Converging Converter Ring with Monolithic Handshake Driving for Next-Generation AI Server,” ESSERC 2026 (Accepted as Lecture).
X. Wang et al., “A 6-A 93.8%-Peak-Efficiency 5V-to-Sub-1V Segment-Interlaced SC-Parallel-Inductor Converter Featuring Inherently Balanced Ganging for Wafer-Scale Computing System,” IEEE JSSC (Early Access), Aug. 2026.
Serving as Session Chair at the IEEE Workshop on Control and Modeling for Power Electronics (COMPEL) 2026.
X. Wang et al., “Algebraic Synthesis for A Family of Inherently Balanced Multi-Phase Hybrid Switched-Capacitor Converters…,” COMPEL 2026 (Accepted as Poster).
X. Wang et al., “Geometrical State-Plane Analysis of GaN-Based Buck Converters with Auxiliary-Assisted Zero-Voltage Switching,” COMPEL 2026 (Accepted as Lecture).
Serving as reviewer for IEEE Transactions on Power Electronics (TPEL).
R. Chen, …, X. Wang, et al., “A Triple-Path Resonant-Tracked Voltage Regulator with Package Inductor for System-on-Wafer Vertical Power Delivery,” ISPSD 2026.
Y. Liu, …, X. Wang, et al., “A 200kHz Self-Powered Isolated Gate Driver for SiC and IGBT…,” CICC 2026.
X. Wang et al., “Unicorn: A Unified Clock-and-Power SoC with RL-Adapted Digital SIMO Control and In-TRO Frequency Boosting for Edge Computing,” CICC 2026.
H. Wang, …, X. Wang, et al., “A 1295W/in³ 160A Quad-Phase VPD Module with Flexible Ganging…,” APEC 2026.
H. Wang, …, X. Wang, et al., “Current–Temperature–Resistance Modeling and Conversion Loss Sharing Methodology…,” APEC 2026.
H. Wang, …, X. Wang, et al., “A 30-60V Input 6V Output Regulated Resonant SC Converter… Achieving 100A and 1339W/in³,” APEC 2026.
X. Wang et al., “A Multi-Resonant Cascaded Series-Parallel Switched-Capacitor Converter Featuring Continuously Scalable Conversion Ratio,” APEC 2026, pp. 2097–2103.
X. Wang et al., “X-ReLA: a Family of Stacked-Ladder Charge-Cross-Converging ReSC with 98.2% Peak Efficiency…,” APEC 2026, pp. 3314–3320.
Vertical Power Delivery (VPD) for 2.5D/3D integration; high-density Intermediate Bus Converters (IBC) and PoL regulators; flip-chip PMIC & SiP for AI accelerators and data centers; package-integrated multiphase IVRs.
Hybrid/Resonant SC converters and trajectory-based soft switching; Digital Control, MPC, and RL for transient/efficiency optimization; SIMO converters with advanced cross-regulation suppression.
Instruction-driven adaptive clocking; DVFS and MEP tracking for ULP systems; DLDOs and unified voltage-and-frequency regulators (UVFRs).
H. Zhang, …, X. Wang, et al., “A Discontinuously Resonant Operation for Continuously-Scalable-Conversion-Ratio Switched Capacitor Converter…,” APCCAS 2025.
Power Side-Channel Attack mitigation at circuit level; voltage-stacked power delivery; piezoelectric-resonator-based DCDC; power-timing coordination for In-Memory Computing (IMC).
Y. Wang, X. Wang, et al., “A Capacitorless Fully Synthesizable Digital-LDO…,” EDSSC 2025.
X. Sun, X. Wang, et al., “A 10W 3.8-5V Input IVR Chiplet with 93%-Peak-Efficiency and 3.2A/mm² Density…,” VLSI Technology and Circuits 2025.
F. Tian, …, X. Wang, et al., “E-NPU: A 34~126nJ/Class Event-Driven Adaptive Neural SoC…,” CICC 2025.
H. Wang, X. Wang, Y. Wang, and X. Liu, “Evaluation Index-Based Multiphysics Coupling Model…,” APEC 2025.
H. Wang, X. Wang, Y. Wang, and X. Liu, “A 660W, 96% Efficiency 3D Heterogeneously Integrated Digital DC/DC Power Module…,” APEC 2025.
X. Wang et al., “Concurrent Charge Distribution and Time-Optimal Control for Unordered Single-Inductor Dual-Output Converter,” APEC 2025, pp. 2675–2680.
X. Sun, J. Yu, X. Wang, et al., “A 92%-Efficiency 0.828μs Settling Time FC5L Voltage Regulator…,” CICC 2024.
X. Wang, X. Liu, and W.-H. Ki, “A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads,” IEEE TCAS-I, vol. 70, no. 11, pp. 4627–4640, Nov. 2023.
School of Integrated Circuits, Tsinghua University. Awards: Beijing Municipal NSF (PI, Grant No. 4244106, 2023–2025); NSFC Key Participant (62374100); National Key R&D Key Participant (2022YFB4401100); National Program for Recruiting Overseas Postdoctoral Talent; Shuimu Tsinghua Scholarship (2023–2026).
Shuimu Tsinghua Scholarship (Global Recruitment) and National Program for Recruiting Overseas Postdoctoral Talent (2023–2026).
X. Wang and W.-H. Ki, “A 65-nm Clock-Domain-Crossing Controller for Digital LDO Regulator with 1.7-ns Response Time,” APCCAS 2022.
X. Wang, W.-H. Ki, and P. K. T. Mok, “A Self-Clocked TDC-Based Unified Clock and Voltage Regulator…,” A-SSCC 2022.
X. Wang and W.-H. Ki, “Partitioning Scheme and Performance Analysis of Distributed Digital Low-Dropout Regulators in SoC,” ISCAS 2022.