Chip Gallery

Tape-out prototypes and measured silicon from PMIC, IVR, and power-converter projects.

SCSL
SCSL
Figure 1 — JSSC 2026

Switched-Capacitor-Stack-Inductor Volumetric IVR with Auxiliary-Assisted Gain Boosting for High-Density PoL Applications [J2].

JSSCChip Gallery
SI-SCPL
SI-SCPL
Figure 2 — JSSC 2026

6-A 93.8%-Peak-Efficiency Segment-Interlaced SC-Parallel-Inductor Converter for Wafer-Scale Computing [J3].

JSSCChip Gallery
ReLA
ReLA
Figure 3 — ESSERC 2026

96.6%-Peak-Efficiency Resonant-Tank Converter with RDL Trace Inductor and Trajectory Control for Vertical Power Delivery [C2].

ESSERC 2026Chip Gallery
Mobius
Mobius
Figure 4 — ESSERC 2026

Mobius: A 12V-to-1V Charge-Cross-Converging Converter Ring with Monolithic Handshake Driving for Next-Generation AI Server [C1].

ESSERC 2026Chip Gallery
Unicorn
Unicorn
Figure 5 — CICC 2026

Unicorn: A Unified Clock-and-Power SoC with RL-Adapted Digital SIMO Control and In-TRO Frequency Boosting for Edge Computing [C8].

CICC 2026Chip Gallery
UVFR
UVFR
Figure 6 — TCAS-I 2023

A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads [J1].

TCAS-IChip Gallery